TUTORIALS

The Committee of the 2017 IEEE NEWCAS Conference will organize 3-hours tutorials on Sunday, June 25, 2017.

Morning tutorials

- 9:00 am to 12:00 am -

T1  –  CMOS circuits for low-power optical receivers
          by Glenn Cowan (ECE, Concordia University – QC, Canada)

      Abstract

      This tutorial will review the basics of optical communication for non-return-to-zero data before discussing traditional optical receiver designs. Limits and trade-offs for transimpedance gain and bandwidth will be covered. The growing range of equalizer-based receivers will be introduced including discrete-time equalizers, continuous-time linear equalizers and decision-feedback equalizers. Noise analysis in this context will be discussed.

      Biography

      Glenn E. R. Cowan received the B.A.Sc. degree from the University of Waterloo, Waterloo, ON, Canada in 1999, and the M.S. and Ph.D. degrees from Columbia University, New York, NY, in 2001 and 2005, respectively. During his graduate studies, he interned with Philips Research, Briarcliff Manor, NY. In 2005, he joined the Communications Technology Department at the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research activities included CMOS circuits for high-speed communications, design for manufacturability, and circuits for the measurement of process variability.
      In 2007, he joined the Department of Electrical and Computer Engineering at Concordia University in Montreal, QC, Canada, where he is an Associate Professor. At Columbia, Dr. Cowan was a 2003 recipient of Analog Device’s Outstanding Student Designer Award. He was the 2005 recipient of Columbia’s Eliahu I. Jury award for outstanding achievement by a graduate student in the areas of systems, communications, or signal processing. His current research activities include low-power mixed-signal circuits for wireless, wireline, and optical communication, as well as mixed-signal computation.

T2  – Introduction to machine learning and (deep) neural networks
          by Anne Jeannin-Girardon (ICube, University of Strasbourg – France)

      Abstract

      Machine learning algorithms are used to give computers the ability to learn without being explicitly programmed. Applications range from self-driving cars, speech and text recognition, semantic web, etc. to data mining in general. This tutorial aims at providing an insight about machine learning techniques by covering different classes of problems and their dedicated solutions through supervised learning and unsupervised learning. In particular, a focus will be put on neural networks : we’ll discuss these architectures and associated algorithms and some applications cases in the form of a lab session. Discussions will also include a hardware consideration regarding the implementation of neural networks, in order to gain some understanding about the inherent constraints of such algorithms in terms of memory and computing power and how we can cope with these constraints using Graphics Processing Units (GPUs).

      Biography

      Anne Jeannin-Girardon received the PhD degree in computer science from the University of Western Brittany, Brest, France, in 2014 where she worked on the design of software architectures dedicated to the use of multi-core devices such as Graphics Processing Units for the modeling and the simulation of complex systems. In 2015, she joined the department of Applied Mathematics and Statistics of the State University of New York at Stony Brook as a postdoctoral associate. Her research interest included complex systems modeling as well as the conception of bio-informatics pipeline for high-throughput sequencing data analysis.
      She joined the University of Strasbourg as an Associate Professor in 2016. She now specializes in the study of complex systems through the use of machine learning techniques. Her domains of applications range from the development of massively parallel computational ecosystems dedicated to deep learning, to health and educational ecosystems.

Afternoon tutorials

- 2:00 pm to 5:00 pm -

T3 – One model to program them all: OpenCL for CPU, GPU and FPGA
          by Franz Richter-Gottfried (Friedrich Alexander University, Erlangen-Nürnberg, Germany)

      Abstract

      OpenCL promises a uniform programming model for different hardware. Drivers are available for CPUs, integrated and dedicated GPUs, and even FPGAs to execute the very same code on very different hardware, with the possibility to use target-specific optimization to exploit the architecture’s characteristics. Without having to write all new code, algorithmic peculiarities can be easily investigated and compared on different hardware, e.g., to chose the hardware which meets the requirements best.
      OpenCL also allows different hardware to collaborate. Heterogeneous platforms, e.g., a CPU supported by a GPU, offers fast and efficient solutions to many problems. Using an FPGA instead of a GPU may even be more efficient because only resources needed on the chip are active, however designing problem specific hardware is challenging and time consuming. High level synthesis with OpenCL tries to ease this by deducing the synthesizable hardware from a description of the system’s
      behavior.
      The tutorial first explains the basic concept of OpenCL, the problem space and the abstract view on physical resources of CPUs, GPUs and FPGAs. Tasks like data transfer, synchronization or design optimization are conveyed with comprehensible examples, leveraging unique features of the architectures.

      Biography

      Franz Richter-Gottfried received his diploma (M.Sc.) with distinction in Computer Science from the Friedrich-Alexander-University Erlangen-Nürnberg (FAU), Germany, in 2011. Since then, he works at the Chair for Computer Architecture, FAU. His research is focused on high level FPGA design for embedded and high-performance computing. His publications deal with OpenCL in general [1] as well as using OpenCL for FPGA design [2]. His teaching experience includes classes in basic computer architecture for undergraduate students and workshops on performance engeneering [3] and OpenCL.
      [1] Richter-Gottfried Franz, Kreutzer Patrick, Ditter Alexander, Schneider Max, Fey Dietmar, “C++ Classes and Templates for OpenCL Kernels with PATOS”, Proceedings of the 4th International Workshop on OpenCL (IWOCL ’16, Vienna, Austria), New York, NY, USA: ACM, 2016. – ISBN 978-1-4503-4338-1
      [2] Richter-Gottfried Franz, Fey Dietmar, “Cellular Neural Networks for FPGAs with OpenCL”, CNNA 2016; 15th International Workshop on Cellular Nanoscale Networks and their Applications, 23-25 Aug. 2016
      [3] Hofmann Johannes, Richter-Gottfried Franz, “Performance-Engineering-Techniken für moderne Multi- und Manycore-Systeme. Talk: Softwarekonferenz für Parallel Programming, Concurrency und Multicore-Systeme, d.punkt Verlag, Heidelberg, 8.4.2016

T4 – Design Automation for Quantum Computing
          by Mathias Soeken, (Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland)

      Abstract

      Quantum computing is getting real. Last year, researchers have fabricated quantum computers that implement well-known quantum algorithms reliably [6] or perform practical applications such as high-energy physics simulation [10] and electronic structure computation [13]. Since all such examples involve circuits of very limited depth, hand designed circuits suffice. This year is predicted to be the year in which quantum computing moves from pure science towards engineering [4], mainly due to the advances in fabricating universal quantum computers [7] in the labs of Google [2, 9] and Microsoft [12]. Since as a result quantum computers scale up, design automation is necessary in order to fully leverage the power of this emerging computational model.
      In order to be prepared for a broader availability of quantum computers, researchers from academia and industry are developing software chains in order to program quantum computers (see, e.g., Microsoft LIQUiji and Quipper [8]). These programs take as input a quantum algorithm, written as a software program, and translate it into quantum gate networks. Fundamental differences between quantum and classical computing pose serious design challenges. One is that the basic fault-tolerant gate sets do not include a universal set of classical gates as fundamental instructions. Instead, one can implement a universal set of reversible gates by applying a so-called T gate to the underlying quantum bits (or qubits, or lines). This gate is sufficiently expensive [1] that it is customary to neglect all other gates when costing a quantum algorithm. Decomposing the reversible logic that arises in such algorithms into quantum gate networks that minimize T gates and qubits is therefore a central challenge in quantum computing.
      This tutorial will give an introduction into the whole design flow and demonstrates how a Verilog gate level design can be translated into quantum gate network. During this demonstration several algorithms from classical and reversible logic synthesis are explained (including algorithms proposed in [11, 5, 14, 16, 17]). The tutorial will only use algorithms for which open source implementations are available (e.g., RevKit [15] and ABC [3]), and show their usages during the talk. This allows the participants to repeat the design flow on their own computers with their own designs. After the tutorial, the participants will have a good understanding of today’s design flow for the technology-independent part to implement quantum algorithms as well as a good overview of existing algorithms and tools. The tutorial will close with open questions and next challenges in the eld.

      References
      [1] M. Amy, D. Maslov, M. Mosca, and M. Roetteler. A meet-in-the-middle algorithm for fast synthesis of depth-optimal quantum circuits. IEEE Trans. on CAD of Integrated Circuits and
      Systems, 32(6):818{830, 2013.
      [2] R. Barends et al. Digitized adiabatic quantum computing with a superconducting circuit. Nature, 534(7606):222{226, 2016.
      [3] R. K. Brayton and A. Mishchenko. ABC: an academic industrial-strength veri cation tool. In Computer Aided Veri cation, pages 24{40, 2010.
      [4] D. Castelvecchi. Quantum computers ready to leap out of the lab in 2017. Nature, 541(7635):9{10, 2017.
      [5] A. De Vos and Y. Van Rentergem. Young subgroups for reversible computers. Advances in Mathematics of Communications, 2(2):183{200, 2008.
      [6] S. Debnath, N. M. Linke, C. Figgatt, K. A. Landsman, K. Wright, and C. Monroe. Demonstration of a small programmable quantum computer with atomic qubits. Nature, 536:63{66, 2016.
      [7] E. Gibney. Physics: Quantum computer quest. Nature, 516(7529):24{26, 2014.
      [8] A. S. Green, P. L. Lumsdaine, N. J. Ross, P. Selinger, and B. Valiron. Quipper: a scalable quantum programming language. In ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 333{342, 2013.
      [9] J. Kelly et al. State preservation by repetitive error detection in a superconducting quantum circuit. Nature, 519(7541):66{69, 2015.
      [10] E. A. Martinez, C. A. Muschik, P. Schindler, D. Nigg, A. Erhard, M. Heyl, P. Hauke, M. Dalmonte, T. Monz, P. Zoller, and R. Blatt. Real-time dynamics of lattice gauge theories with a few-qubit quantum computer. Nature, 534:516{519, 2016.
      [11] D. M. Miller, D. Maslov, and G. W. Dueck. A transformation based algorithm for reversible logic synthesis. In Design Automation Conference, pages 318{323, 2003.
      [12] V. Mourik, K. Zuo, S. M. Frolov, S. R. Plissard, E. P. A. M. Bakkers, and L. P. Kouwenhoven. Signatures of Majorana fermions in hybrid superconductor-semiconductor nanowire devices. Science, 336(6084):1003{1007, 2012.
      [13] P. J. J. O’Malley et al. Scalable quantum simulation of molecular energies. Physical Review X, 6:031007, 2016.
      [14] M. Soeken, G. W. Dueck, and D. M. Miller. A fast symbolic transformation based algorithm for reversible logic synthesis. In Int’l Conf. on Reversible Computation, pages 307{321, 2016.
      [15] M. Soeken, S. Frehse, R. Wille, and R. Drechsler. RevKit: A toolkit for reversible circuit design. Multiple-Valued Logic and Soft Computing, 18(1):55{65, 2012.
      [16] M. Soeken, M. Roetteler, N. Wiebe, and G. De Micheli. Design automation and design space exploration for quantum computers. In Design, Automation and Test in Europe, 2017.
      [17] M. Soeken, R. Wille, O. Keszocze, D. M. Miller, and R. Drechsler. Embedding of large Boolean functions for reversible logic. ACM Journal on Emerging Technologies in Computing Systems, 12(4):41:1{41:26, 2016.

      Biography

      Mathias Soeken works as a researcher at the Integrated Systems Laboratory at EPFL, Lausanne, Switzerland in the group of Giovanni De Micheli. From 2009 to 2015 he worked at the University of Bremen, Germany in the group of Rolf Drechsler. Since 2014, he is a regularly visiting post doc at UC Berkeley, CA, USA in the group of Robert K. Brayton. He holds a Ph.D. degree (Dr.-Ing.) in Computer Science from University of Bremen, Germany (2013). His research interests are logic synthesis, reverse engineering, formal veri cation, and quantum computing. He is involved in active collaborations with the quantum architectures and computation group at Microsoft Research. He is maintaining the logic synthesis frameworks CirKit and RevKit. Dr. Soeken received a scholarship from the German Academic Scholarship Foundation, Germany’s oldest and largest organisation that sponsors outstanding students in the Federal Republic of Germany. He has been serving as TPC member for several conferences, including DAC’17 and ICCAD’17 and is reviewer for Mathematical Reviews as well as for serveral journals.

T5 – Introduction to Audio Steganography and Watermarking for Information Hiding
          by Kaliappan Gopalan, Dept of Electrical and Computer Engineering, Purdue University Northwest, Hammond, Indiana, USA)

      Abstract

      Information hiding and steganography are concerned with embedding information in a media (cover) signal in an imperceptible manner. Applications of steganography include watermarking for copyright protection and authentication, data hiding for secure storage and transmission, and covert communication using unclassified channels. Indiscernible hiding of information in an audio signal is more challenging than invisible modification of an image or video signal due to the wide dynamic range of human audibility in frequency and power level. In spite of this challenge, human auditory system imperfections, which lead to psychoacoustic masking effects in hearing and perception, can be exploited for unnoticeable modifying of a cover audio signal in accordance with a given piece of covert information. Since the modification is carried out in the masked regions of perceptibility, the information-embedded audio (stego) signal appears to be the same as the original signal in spectrogram and perceptual quality. Successful embedding depends, among others, on the discernibility of any difference between the original cover signal and the stego signal, robustness of the hidden information to noise, and recovery key that does not require the original cover audio signal.
      This presentation will provide an overview of psychoacoustic masking-based audio steganography with an emphasis on the newly developed tone insertion techniques in the spectral and cepstral domains, and their extension to image embedding. Robustness of hidden data to noise and attacks, and quantitative measures for perceptual difference will also be discussed. Extension of tone insertion steganography for hiding data on images will be illustrated.

      Biography

      K. ‘Gopal’ Gopalan has been a professor of Electrical and Computer Engineering at Purdue University Northwest, Hammond, Indiana since 1985. He has been awarded the Outstanding Sponsored Research Scholar Award in 2009 and the Outstanding Faculty Scholar Award in 2002 and 2010, all at Purdue University Calumet.
      From 1987 to 1995 he conducted research in the areas of signal and image processing for nondestructive evaluation of advanced materials at Argonne National Laboratory, Argonne, Illinois, first as a summer faculty research participant and later as a consultant. In addition, he has been a summer faculty research associate at Wright-Patterson Air Force Base, Ohio, and the Air Force Research Laboratory (AFRL), Rome, New York. His research in speech analysis, speaker recognition, audio steganography, and keyword recognition has been funded by AFRL, Rome, NY. He has received three U.S. patents, all on audio steganography and data embedding.
      Gopalan gave keynote addresses on Keyword Spotting in Speech Communication – An Overview at (a) the 8th International Conference on Computing, Communications and Control Technologies, Orlando, FL, in April 2010, and (b) the International Workshop on Multimedia Streaming, Kochi, India, in July 2011. He presented tutorials on (a) Audio watermarking and steganography, at the 55th International Midwest Symposium on Circuits and systems (IEEE MWSCAS 2012), Boise, Idaho, in August 2012, (b) Audio Steganography for Watermarking, Data Embedding and Covert Communication, at the 15th IASTED International Conference on Signal and Image Processing, Banff, Canada, in July 2013, (c) Introduction to Information Hiding in Audio Signals with an Extension to Image Steganography, at the Eleventh Advanced International Conference on Telecommunications (AICT 2015), Brussels, Belgium, in June 2015, and (d) Introduction to Information Hiding in Audio Signals with an Extension to Image Steganography, at the IEEE ComSoc Meeting, MILCOM 2015, Tampa, FL, in October 2015. He also presented a one-hour talk on Information Hiding in Audio Signals at the IEEE Chicago Section meeting in November 2012. In addition, he has given several invited presentations at universities and colleges in Australia, India, Malaysia and Singapore.
      Gopalan is a Life Senior Member of the IEEE and is the author of two textbooks, Introduction to Digital Microelectronic Circuits (Irwin/McGraw-Hill, 1996), and Introduction to Signal and System Analysis (Cengage, 2009).